Now you have compiler fundamentals down pat, let's move on to some of the techniques you can use to improve the parser's design and performance.

ALAMEDA, CA--(Marketwired - Aug 13, 2013) - Verific Design Automation (www.verific.com), provider of SystemVerilog, Verilog and VHDL parsers, today announced that Tabula (www.tabula.com) has added ...

SANTA CLARA, Calif. -- June 5, 2013 – Tabula Inc., advancing high-performance programmable logic solutions for network infrastructure systems, today announced the availability of the latest addition ...

Now, it's time to discuss a few techniques to improve the overall design of the parser. I'll cover performance, general structure and what can be done to considerably ...