Design-Reuse1 个月
DDR DLL IP, 200MHz - 400MHz, Output: 25% Delay, UMC 0.11um HS/AE process
DLL-based cell that generates two-channel DQS with 25% timing delay for DDR2 SDRAM controller usage, UMC 0.11um HS/AE (AL Advanced Enhancement) Logic process.
Design-Reuse3 年
Delay cell IP Listing
DLL-based cell that generates 32 phase delay for FTSDC021; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process The OT3910 is a set of cells for implementing 800Mb DDR (400MHz) LVDS IO in 180n ...