That's what one-time IP provider Leopard Logic Inc. plans to do late this year or early next year when it rolls out its “hybrid” programmable chips, mixing elements of FPGA and ASIC design.

Programmable logic is slower and much larger than comparable standard-cell functions. Yet, it delivers reconfigurability—i.e., the ability to reconfigure the logic design on a finished chip.

(1) Deep analysis of chip design. The authors dissect the commonly adopted process of chip design and analyze the key steps in different design stages (i.e., logic design, circuit design, and ...

Here are six tips and tricks that can be used to improve the speed of a chip design and reduce delay within the design at higher frequencies.

It’s an elegant design, with six seven-segment displays, a time base derived from line frequency, controlled entirely by 74-series logic chips. There was only one problem with it: it kinda sucked.

As the system-on-a-chip (SoC) era marches forward, there's a pressing need to embed large amounts of memory onto a logic chip and make the resulting technology as flexible and cost-effective as ...

India is a key hub for chip design, hosting 20% of the world's engineers in the field. Global tech giants have established ...

When the computer gets busy, the wires connecting logic and memory get jammed. A new approach would build layers of logic atop layers of memory to create tightly interconnected high-rise chips.

Memory capacity also scales impressively. Across a pod, Ironwood offers 1.77PB of directly addressable HBM. That level sets a ...