That's what one-time IP provider Leopard Logic Inc. plans to do late this year or early next year when it rolls out its “hybrid” programmable chips, mixing elements of FPGA and ASIC design.

(1) Deep analysis of chip design. The authors dissect the commonly adopted process of chip design and analyze the key steps in different design stages (i.e., logic design, circuit design, and ...

Chip design is as much of an art as it is an engineering feat. With all of the possible layouts of logic and memory blocks and the wires linking them, there are a seemingly infinite placement ...

In today’s highly competitive semiconductor industry, chip-design companies strive for competitive advantages by optimizing designs for PPA (Power, Performance, Area). Along with the functional logic, ...

Built on TSCM’s 7nm process, AMD claims its new Versal Premium VP1902 adaptive SoC is the world’s largest, offering 18.5 million logic cells for 2X the programmable logic density and also ...

The RISC-V architecture is inexorably inching from its theoretical origins towards the mainstream, as what could once only be done on an exotic FPGA can now be seen in a few microcontrollers as wel… ...

Programmable logic is slower and much larger than comparable standard-cell functions. Yet, it delivers reconfigurability—i.e., the ability to reconfigure the logic design on a finished chip.

Here are six tips and tricks that can be used to improve the speed of a chip design and reduce delay within the design at higher frequencies.

Advanced Packaging Design For Heterogeneous Integration Traditional chips are transforming into smaller, well-partitioned chiplets that require chip-to-chip interconnections.