So the code instructs the FPGA (or, more accurately, the Verilog compiler) to examine the number and set dispoutput based on the input. The <= character, by the way, are a non-blocking assignment.

This paper focuses on the implementation and simulation of 4-bit, 8-bit and 16-bit carry look-ahead adder based on Verilog code and compared for their performance in Xilinx.

With Verilog, you generally won’t create flip flops directly, but will let the compiler infer them from your code. Let’s jump right in with some examples.